EECC 631 Advanced VLSI Design

EECC 731 VLSI Design Projects

Dr. Ken Hsu

Instructions to use Synopsys DesignWare Library in ModelSim Simulation

ModelSim Simulation with Synopsys Library:  DesignWare

The Models can be found in the following directories:

VHDL models can be found at:

/tools/synopsys/syn/current/dw/dw0#/src/*

Replace the # with a number from 1 to 6.

For a particular number, see the DesignWare library reference manual in the VLSI Design Lab. You can instantiate those compoenents and use structural VHDL codes.

You may try infer to see if you will work in the ModelSim environment.

Verilog models can be found at:

/tools/synopsys/syn/current/dw/sim_ver

You may infer or instantiate those components in your design, just like you write models yourself.

In the VHDL or verilog modeling source coce, specify all the libraries that you want to use, for example:

library ieee;

  use ieee.std_logic_1164.all;

  use ieee.std_logic_unsigned.all;

  use ieee.numeric_std.all;

use work.DW_foundation_arith.all;

use work.DW.ctrl_constraint.all;

In your source code, you can copy the source code, e.g.,

component dw_div_oper                      #( from DesignWare)

            Port( a                                      :in std_logic_vector(63 downto 0);

                     b                                     :in std_logic_vector(63 downto 0);

                     quotient_uns                    :out std_logic_vector(63 downto 0);

                     quotient_tc                      :out std_logic_vector(63 downto 0);

                     quotient_uns                    :out std_logic_vector(63 downto 0);

                     quotient_tc                      :out std_logic_vector(63 downto 0);

end component;                                    :

Then use the structural modeling to make the port connections.

If you have any questions, please email Charles Gruener at cjg9411@rit.edu,  System Adminstrator for the library directory path and DW components. Or Call Dr. Ken Hsu 475-2655, or send him an email at kwheec@rit.edu

I would like to thank David Chandler and Alex Braun for their contributions for the above  instructions.

Ken Hsu